An integrated semiconductor memory, for example, a DRAM (dynamic random access memory) semiconductor memory, generally comprises a plurality of memory banks in which memory cells are arranged at a crossover point between a word line and a bit line. FIG. 1 shows an integrated semiconductor memory 100 with memory banks 10a, 10b, 10c. A small detail from a DRAM memory cell array is illustrated in the memory bank 10a. For simplicity, two memory cells SZa and SZb are illustrated in the memory cell array of the memory bank 10a. The memory cells comprise a selection transistor Ata, ATb and a storage capacitor SCa and SCb. The selection each have a control terminal STa, STb connected to a word line WL1. By driving the word line with a first level of a control voltage VPP1 or a second level of a control voltage VPP2, which are generated by a circuit 20 for generating the control voltage, the selection transistors of the memory cells, whose control terminals are connected to the word line, are turned off or turned on, respectively.
The bit lines BL1, BL2 are, respectively connected to a sense amplifier 11a and a sense amplifier 11b within the memory bank 10a. In addition, the sense amplifiers are each connected to a terminal for application of a reference voltage Vref. On the output side, the sense amplifiers are connected to data inputs and outputs DQA1, DQA2. In order to read an item of information into and out of a memory cell, the memory bank associated with the corresponding memory cell are selected and the word line connected to the control terminal of the memory cell. For this purpose, address signals AS1, AS2, . . . , ASn are applied to input terminals E80a, E80b, . . . , E80n of an address register 80. By the address signals AS1, AS2, . . . , ASn, a memory bank address BA10a, BA10b, BA10c for selecting the memory banks 10a, 10b, 10c and a word line address, for example a word line address WLA1 for selecting the word line WL1, and a bit line address, for example, a bit line address BLA1 for selecting the bit line BL1, in the address register 80 are stored. By a column decoder 91, the word line associated with the word line address WLA1 can be selected and driven with the control voltage VPP1 or VPP2. The bit line associated with the bit line address BLA1 can be selected by a row decoder 92. The memory cell located at the crossover point between the selected word and bit lines can be connected to one of the data inputs and data outputs for reading items of information in and out.
A write and read access to the memory cell SZa located at the crossover point of the word line WL1 and the bit line BL1 will be considered in greater detail below. By driving the word line WL1 with a high level of the control voltage VPP1, the selection transistor ATa of the memory cell SZa is turned on. If a logic 1 information item is intended to be written to the memory cell SZa, the sense amplifier 10a generates a high signal level on the bit line BL1, or a low signal level if a logic 0 information item is intended to be stored in the memory cell SZa. Accordingly, the storage capacitor SCa is charged to a high or a low signal level, respectively.
In order to read out an item of information from the memory cell SZa, all the storage capacitors of memory cells within the memory bank 10a are isolated from the associated bit lines. For example, if the memory cell SZa located in the memory bank 10a is intended to be read, then the memory bank 10a is selected by a memory bank address BA10a present at the address register 80. The word lines of the selected memory bank 10a are subsequently driven with a low level of the control voltage VPP2, so that the selection transistors of the memory cells are turned off. If the bit lines of the memory bank 10a are isolated from their associated memory cells, the bit lines are short-circuited among one another by a precharge circuit 12 and connected to a precharge potential VBLEQ via a terminal A2a of the memory bank 10a. After a defined precharge time, the bit lines of the memory bank 10a are charged to the common precharge potential VBLEQ. This precharge procedure is intended to prevent an undefined potential state present on the bit lines from adversely influencing a subsequent read-out procedure for the storage capacitors of the memory cells.
After the defined precharge time has elapsed, the memory cell SZa is conductively connected to the bit line BL1 again. In this case, the word line WL1 in the memory bank 10a is selected by the memory bank address BA10a present at the address register 80 and the word line address WLA1. After driving the selected word line WL1 in the selected memory bank 10a with the high level of the control voltage VPP1, the selection transistor ATa is turned on and the storage capacitor SCa is conductively connected to the bit line BL1. The voltage level stored on the storage capacitor SCa generates a potential increase or potential decrease on the bit line BL1. The potential increase or decrease with respect to the precharge potential VBLEQ is amplified by the sense amplifier 11a through comparison with the reference voltage Vref to form a high or low signal level at the data output DQA1.
The integrated semiconductor memory 100 furthermore has a buffer circuit 30 with input terminals E30a, E30b, . . . E30n for applying input signals ES1, ES2, . . . , ESn. The input signals are control signals which are applied externally for controlling the integrated semiconductor memory and are buffer-stored in the buffer circuit 30. The integrated semiconductor memory furthermore has a control circuit 50 with a first control terminal S50a for applying a control clock CLK. The control circuit 50 generates an internal control clock iCLK from the externally applied control clock CLK, circuit components of the integrated semiconductor memory being driven with the internal control clock. In the case of a synchronously operated integrated semiconductor memory, for example, an SDRAM (synchronous dynamic random access memory) semiconductor memory, the input signals ES buffer-stored in the buffer circuit, when the buffer circuit 30 is driven with the internal control clock iCLK, upon rising and falling edges of the internal control clock in each clock period, are transferred to a command decoder circuit 40 and decoded there. After the input signals have been decoded, the command decoder circuit 40, depending on the input signal, generates a first control signal S1, a second control signal S2, a third control signal S3, a fourth control signal S4, and a fifth control signal S5, which drive the control circuit 50 upon a clock edge of the control clock CLK. The first and second control signals S1 and S2 are buffer-stored in a command register 70 when the command decoder circuit 40 is driven with the internal control clock. For this purpose, the command decoder circuit 40 is directly connected to the command register 70 via the signal path illustrated by a dashed line. The first and second control signals S1 and S2 are transferred to the command register 70 upon the clock edges of the internal control clock iCLK with which the command decoder circuit 40 is driven by the control circuit 50. The significance of the individual control signals will be discussed in more detail in the description of FIGS. 2 and 3.
From the control signals fed to the control circuit 50 by the command decoder circuit 40, the control circuit 50 generates an internal command signal KS, with which the command register 70 is driven, upon the rising clock edge of the control clock CLK. If, depending on the input signals ES1, . . . , ESn applied to the input terminals E30a, . . . , E30n, the first and second control signals S1 and S2 from the command decoder circuit 40 have been buffer-stored in the command register 70, by driving the command register 70 with an internal command signal KS, the control signals S1 and S2 buffer-stored in the command register 70 are fed to the circuit 20 for generating the control voltage VPP1 and VPP2 for controlling the selection transistors. The circuit 20 for generating the control voltage generates on the output side, the first level of the control voltage VPP1 and the second level of the control voltage VPP2, which is fed via a terminal A1 to the word line, selected by the word line address WLA, in the memory bank selected by the memory bank address BA. The first level VPP1 and the second level VPP2 of the control voltage serve for turning on and turning off, respectively, the selection transistors of the memory cells in the selected memory bank.
FIG. 2 shows, in a signal state diagram, the control signals S1, S2, S4, S5 fed to the control circuit 50 by the command decoder circuit 40 during a write, precharge, and read procedure. In the event of a state change in the first control signal S1, the selection transistors connected to the selected word line in the selected memory bank are turned on. A state change in the second control signal S2 causes the selection transistors in the selected memory bank to be turned off. In the event of a state change in the fourth control signal S4, an item of information is written to a memory cell. In the event of a state change in the fifth control signal S5, an item of information is read out from a memory cell.
FIG. 2 furthermore illustrates four clock periods of the control clock CLK having the period duration TP. Moreover, the profile of the control voltage VPP and the profile of the data signals DQ present at the data inputs and outputs are also illustrated besides the profile of the control signals.
In the first clock period 1 of the control clock, a write access is effected, which is indicated to the control circuit 50 by the command decoder circuit 40 by means of the state change in the fourth control signal S4. The first control signal S1 is transferred into the command register 70 by the command decoder circuit 40. Upon a clock edge of the external control clock CLK, the control circuit 50 drives the command register 70 with the command signal KS. The first control signal S1 buffer-stored in the command register 70 thereupon drives the circuit 20 for generating the control voltage VPP. As a result, the selection transistors that are connected via their respective control terminals to a selected word line in a selected memory bank are turned on in order that an item of information can be stored in at least one of the memory cells. The selected word line is therefore driven with the high level of the control voltage VPP1 by the circuit 20 for generating the control voltage VPP at the instant t1, which corresponds to the rising clock edge of the control clock CLK. At the instant t12 during the first clock period of the control clock CLK, data signals DQ are applied to the data inputs. Upon the rising clock edge at the beginning of the second clock period 2 of the control clock at the instant t2, no control signals are applied to the control circuit 50. The read-in procedure for the data signals DQ is concluded at the instant t21 within the second clock cycle of the control clock. At the beginning of the third clock period 3 of the control clock at the instant t3, the selection transistors that were turned on for the read-in procedure in the selected memory bank are turned off again as a result of the control circuit 50 being driven with the second control signal S2 by the command decoder circuit 40. The second control signal S2 is transferred into the command register 70 by the command decoder circuit 40. Upon a clock edge of the external control clock CLK, the control circuit 50 drives the command register 70 with the command signal KS. The second control signal S2 buffer-stored in the command register 70 thereupon drives the circuit 20 for generating the control voltage VPP. The circuit 20 for generating the control voltage VPP thereupon drives the word lines in the selected memory bank with the low level of the control voltage VPP2. In the third clock period, the precharge procedure can thus be effected in that the bit lines which are now isolated from their connected memory cells are short-circuited among one another by means of the precharge circuit 12 and are driven with the precharge potential VBLEQ. The bit lines in the selected memory bank are thus charged to the common precharge potential VBLEQ. Upon the rising clock edge of the control clock at the beginning of the fourth clock period 4 at the instant t4, a read-out procedure from at least one memory cell is effected. This is indicated to the control circuit 50 by the state change in the fifth control signal S5. As a result of the state change in the first control signal S1 upon the rising clock edge at the beginning of the fourth clock period of the control clock, the selection transistors that are connected via the respective control terminals to the selected word line in the selected memory bank are turned on. For this purpose, the control circuit 50 drives the command register 70 with the internal command signal KS again upon the rising clock edge of the control clock in the fourth clock period. The first control signal S1 buffer-stored in the command register 70 thereupon drives the circuit 20 for generating the control voltage VPP, as a result of which the word line selected by means of the corresponding word line address is driven with the high level of the control voltage VPP1 by the circuit 20 for generating the control voltage VPP. At the instant t41 within the fourth clock period of the control clock, the data signals DQ in accordance with the items of information stored in the memory cells to be read occur at the data outputs.
It becomes clear from the state diagram illustrated in FIG. 2 that, in the case of the synchronously operated integrated semiconductor memory, the control circuit 50 executes control procedures that are required for writing items of information to memory cells, for precharging bit lines, and for reading from memory cells, always upon rising clock edges of the control clock CLK. If a synchronously operated semiconductor memory is intended to be tested, clock signals CLK are predefined externally by a test system at the first control terminal S50a of the control circuit 50. However, since control procedures for write, precharge and read procedures in a memory bank of the integrated semiconductor memory are initiated by the control circuit 50 only upon rising clock edges of the control clock or only in each case during a clock period of the control clock, the minimum time between a precharge command, for example, the state change in the second control signal S2 at the beginning of the third clock period of the control clock, and a subsequent read command, for example, the state change in the first control signal S1 and in the fifth control signal S5 at the beginning of the fourth clock period of the control clock, is dependent on the maximum possible clock rate of the test system.
The precharge times TV of an integrated semiconductor memory, in particular, constitute an important time parameter to be specified. The precharge time is the time required to charge the bit lines of a memory bank to the common precharge potential VBLEQ. The precharge procedure is generally initiated after a write or read procedure in the selected memory bank in order that a subsequent write or read procedure is not influenced by an undefined potential state on the bit lines in the selected memory bank. The precharge time TV can thus also be defined as the time between closing the selection transistors that are still turned on from a preceding write or read access and a renewed turn-on of the selection transistors for a subsequent write or read access.
In the testing of integrated semiconductor memories, a distinction is generally made between low-end test systems and high-end test systems. Low-end test systems are generally used to test the effects of ageing processes on the functionality of the integrated semiconductor memory. Such low-end test systems have the advantage that they enable a parallel testing of many semiconductor memories simultaneously. The required test times and also the required test costs associated therewith can be reduced as a result.
Low-end test systems have the disadvantage, however, that they are subject to limitations with regard to the clock rate. In test systems having a parallel capability, the clock rate of the control clock generated by the tester is nowadays of an order of magnitude of 5 MHz. The period duration TP of a clock period thus becomes greater than 200 ns. Such testers can be used to test time parameters, such as the precharge times for example, only with a minimum possible time duration of 200 ns. Since the precharge times in present-day memory modules are generally already specified below 12 ns, however, low-end test systems can no longer be used for testing this critical time parameter or generally have to be furnished with additional equipment that is expensive or has a reduced parallel capability.
A further possibility for testing the specified precharge times consists in using high-end test systems. Such test systems operate at a high frequency and are generally used for very precise time parameter measurements. However, parallel testing of modules is generally not possible with these high-end test systems.
A further limitation of these test systems results from the fact that quite generally only the maximum and also the minimum specification temperature can be tested with the high-end testers. However, a test pass with a low-end test system typically starts with room temperature tests, and even a test having a duration of several minutes is still cost-tenable on account of the parallel capability of the low-end tester. Since the memory modules are also operated at approximately room temperature and for a long time in the applications envisaged for them, a low-end test system having a parallel capability can therefore generally realize test conditions which come significantly closer to the use of the memory modules in an application than is possible with high-end test systems. It is desirable, therefore, to be able to use the low-end testers also for testing particularly short time durations, such as precharge times of less than 12 ns, for example.